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document number : mc10XSC425 rev. 2.0, 9/2013 freescale semiconductor ? advance information * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2013. all rights reserved. quad high side switch ? (dual 10 mohm , dual 25 mohm) the 10XSC425 is one in a family of devices designed for low-voltage lighting or factory automation applications. its four low r ds(on) mosfets (dual 10 m ? /dual 25 m ? ) can control four separate 55 w / 28 w bulbs, and/or xenon module s, and/or leds, and/or dc low voltage motors. programming, control and diagnostics are accomplished using a 16-bit spi interface. its output with selectable slew-rate improves electromagnetic compatibility (e mc) behavior. additionally, each output has its own parallel input or spi control for pulse-width modulation (pwm) control if desired. the 10XSC425 allows the user to program via the spi the fault current trip levels and duration of acceptable inrush. the device has fail-safe mode to provide fail-safe functionality of the outputs in case of mcu damaged. this device is powered by smartmos technology. features ? four protected 10 m ? and 25 m ? high side switches (at 25 c) ? operating voltage range of 6.0 to 20 v with sleep current ? < 5.0 ? a, extended mode from 4.0 to 28 v ?8.0 mhz 16-bit 3.3 v and 5.0 v spi control and status reporting with daisy chain capability ? pwm module using external clock or calibratable internal oscillator with programm able output delay management ? smart overcurrent shutdown, severe short-circuit, overtemperature protections with ti me limited autoretry, and fail- safe mode, in case of mcu damage ? output off or on open-load detection compliant to bulbs or leds and short to battery detection. ? analog current feedback with selectable ratio and board temperature feedback . figure 1. 10XSC425 simplified application diagram high side switch 10XSC425 ek suffix (pb-free) 98asa00368d 32-pin soicw-ep applications ? low-voltage industrial lighting ? halogen lamps ? incandescent bulbs ? light-emitting diodes (leds) ? hid xenon ballasts ? low voltage factory automation mcu 10XSC425 v dd v dd v pwr v dd v pwr wake fsb sclk csb so rstb si in0 in1 in2 in3 csns fsi gnd vdd vpwr hs0 hs1 hs2 hs3 load i/o sclk csb si i/o so i/o i/o i/o i/o a/d gnd load load load free datasheet http:///
analog integrated circuit device data ? 2 freescale semiconductor 10XSC425 free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 3 10XSC425 table of contents 1 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.1output current monitoring (c sns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.2direct inputs (in0, in1, in2, in3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.3fault status (fsb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.4wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.5reset (rstb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.6chip select (csb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.7serial clock (sclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.8serial input (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.9digital drain voltage (vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.10ground (gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.11positive power supply (vpwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.12serial output (so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.13high side outputs (hs3, hs1, hs0, hs2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.14fail-safe input (fsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 functional internal block de scription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.2 high side switches (hs0?hs3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.3 mcu interface and output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 functional device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 spi protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.2normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.3fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.4watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.5normal and fail-safe mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.6fault mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.7start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 protection and diagnostic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3.1protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3.2auto-retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.3diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.4analog current recopy and temperature feedbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.5active clamp on vpwr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 free datasheet http:///
analog integrated circuit device data ? 4 freescale semiconductor 10XSC425 6.3.6reverse battery on vpwr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.7ground disconnect protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.8loss of supply lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.9emc performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.4 logic commands and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.4.1 serial input communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.4.2 device register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.4.3 serial output communication (device status return data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.4.4 serial output bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3 package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 5 10XSC425 1 orderable parts this section describes the part numbers availa ble to be purchased along with their differences. valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to http:// www.freescale.com and perform a part number search for the following device numbers: 07xs and 17xs. table 1. orderable part variations part number (1) temperature (t a ) package quad version mc10XSC425ek -40 to 125c 32 pin soic exposed pad notes 1. to order parts in tape & real, add the r2 suffix to the part number. free datasheet http:///
analog integrated circuit device data ? 6 freescale semiconductor 10XSC425 2 internal block diagram figure 2. 10XSC425 simplified internal block diagram gnd programmable watchdog overtemperature detection logic severe short-circuit selectable overcurrent internal regulator selectable slew rate gate driver over/undervoltage protections hs0 vpwr vdd csb sclk so si rstb wake fsb in0 fsi in3 hs1 hs0 hs1 hs2 hs3 hs2 hs3 in1 in2 detection selectable output csns v reg i dwn i up i dwn r dwn open-load detections detection temperature feedback v reg short to vpwr detection charge v dd failure detection calibratable oscillator pwm module vpwr voltage clamp r dwn current recopy analog mux overtemperature prewarning v dd pump por free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 7 10XSC425 3 pin connections 3.1 pinout diagram figure 3. 10XSC425 pin connections 3.2 pin definitions table 2. 10XSC425 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 28 . pin number pin name pin function formal name definition 1 wake input wake this input pin controls the device mode. 2 rstb input reset this input pin is used to initialize t he device configuration and fault registers, as well as drive the device into a low-current sleep mode. 3 csb input chip select (active low) this input pin is connected to a chip se lect output of a master microcontroller (mcu). 4 sclk input serial clock this input pin is connected to the mcu pr oviding the required bit shift clock for spi communication. 5 si input serial input this pin is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previous device of a daisy - chain of devices. 6 vdd power digital drain voltage this pin is an external voltage input pi n used to supply power interfaces to the spi bus. 7 so output serial output this output pin is connected to the spi se rial data input pin of the mcu or to the si pin of the next device of a daisy - chain of devices. transparent top view of package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 wake rstb csb sclk si vdd so gnd vpwr hs3 hs3 hs3 hs3 hs1 hs1 hs1 fsb in3 in2 in1 in0 csns fsi nc hs2 hs2 hs2 hs2 hs0 hs0 hs0 gnd free datasheet http:///
analog integrated circuit device data ? 8 freescale semiconductor 10XSC425 8, 25 gnd ground ground these pins, internally shorted, are the ground for the logic and analog circuitry of the device. these ground pins must be also shorted in the board. 9, 33 vpwr power positive power supply this pin connects to the positive power supply and is the source of operational power for the device. pins 9 and 33 must be externally connected. 10, 11, 12, 13 hs3 output high side output protected 25 m ? high side power output pins to the load. 14, 15, 16 hs1 output high side output protected 10 m ? high side power output pins to the load. 17, 18, 19 hs0 output high side output protected 10 m ? high side power output pins to the load. 20, 21, 22, 23 hs2 output high side output protected 25 m ? high side power output pins to the load. 24 nc n/a no connect this pin may not be connected. 26 fsi input fail-safe input this input enables the watchdog timeout feature. 27 csns output output current monitoring this pin reports an analog value proportional to the designated hs[0:3] output current or the temperature of the gnd flag (pin 14). it is used externally to generate a ground-referenced voltage for the microcontroller (mcu) . current recopy and temperature fee dback is spi programmable. 28 29 30 31 in0 in1 in2 in3 input direct inputs each direct input controls the device mode. the in[0 : 3] high side input pins are used to directly control hs0 : hs3 high side output pins. the pwm frequency can be generated from in0 pin to pwm module in case of external clock is set. 32 fsb output fault status (active low) this pin is an open drain configured output requiring an external pull-up resistor to vdd for fault reporting. table 2. 10XSC425 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 28 . pin number pin name pin function formal name definition free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 9 10XSC425 4 electrical characteristics 4.1 maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol ratings value unit notes electrical ratings v pwr(ss) vpwr supply voltage range ? load dump at 25 c (400 ms) ? maximum operating voltage ? reverse battery 41 28 -18 v v dd vdd supply voltage range -0.3 to 5.5 v v dig input / output voltage -0.3 to 5.5 v (5) v so so and csns output voltage -0.3 to v dd + 0.3 v i dig digital input/ output current in clamp mode 100 a i cl(wake) wake input clamp current 2.5 ma i cl(csns) csns input clamp current 2.5 ma v hs[0:3] hs [0:3] voltage ? positive ? negative 41 -24 v v pwr - v hs high side breakdown voltage 47 v i hs[0:3] output current 6.0 a (2) e cl [0:1] hs[0,1] output clamp energy using single pulse method 60 mj (3) e cl [2:3] hs[2,3] output clamp energy using single pulse method 25 mj (3) v esd1 v esd2 v esd3 v esd4 esd voltage (v pwr pins 9 and 33 must be externally connected.) ? human body model (hbm) for hs[0:3], vpwr and gnd ? human body model (hbm) for other pins ? charge device model (cdm) corner pins (1, 13, 19, 21) all other pins (2-12, 14-18, 20, 22-24) 8000 2000 750 500 v (4) notes 2. continuous high side output current rating so long as maximum junction temperature is not exc eeded. calculation of maximum ou tput current using package thermal resistance is required. 3. active clamp energy using single-pulse method (l = 2.0 mh, r l = 0 ? , v pwr = 14 v, t j = 150 ? c initial). 4. pins 9 and 33 must be externally connected. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ), the machine model (mm) (c zap = 200 pf, r zap = 0 ? ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 5. input / output pins are: in[0:3], rstb, fsi, si, sclk, csb, and fsb free datasheet http:///
analog integrated circuit device data ? 10 freescale semiconductor 10XSC425 thermal ratings t a t j operating temperature ?ambient ?junction - 40 to 125 - 40 to 150 ? c (5) t stg storage temperature - 55 to 150 ? c thermal resistance r ? jc r ? ja thermal resistance ? junction to case ? junction to ambient <2.5 30 ? c/ w (7) t solder peak pin reflow temperature during solder mounting 260 ? c (8) notes 6. to achieve high reliability over 10 y ears of continuous operation, the device's conti nuous operating junction temperature sho uld not exceed 125 ? ? c. 7. device mounted on a 2s2p test board per jedec jesd51-2. 15 c/w of r ja can be reached in a real application case (4 layers board). 8. pin soldering temperature limit is for 40 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. table 3. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol ratings value unit notes free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 11 10XSC425 4.2 static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions 6.0 v ?? ? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power inputs v pwr battery supply voltage range ? fully operational ? extended mode 6.0 4.0 ? ? 20 28 v (9) v pwr (clamp) battery clamp voltage 41 47 53 v (10) i pwr(on) v pwr operating supply current ? outputs commanded on, hs[0 : 3] open, in[0:3] > v ih ?6.520 ma i pwr(sby) v pwr supply current ? outputs commanded off, off open-load detection disabled, hs[0 : 3] shorted to the ground with v dd = 5.5 v ? wake > v ih or rstb > v ih and in[0:3] < v il ?6.57.5 ma i pwr(sleep) sleep state supply current v pwr = 12 v, rstb = wake = in[0:3] < v il , hs[0 : 3] shorted to ground ?t a = 25 c ?t a = 85 c ? ? 1.0 ? 5.0 30 ? a v dd(on) v dd supply voltage 3.0?5.5 v i dd(on) v dd supply current at v dd = 5.5 v ? no spi communication ?8.0 mhz spi communication ? ? 1.6 5.0 2.2 ? ma (11) i dd(sleep) v dd sleep state current at v dd = 5.5 v ??5.0 ? a v pwr(ov) overvoltage shutdown threshold 28 32 36 v v pwr (ovhys) overvoltage shutdown hysteresis 0.2 0.8 1.5 v v pwr(uv) undervoltage shutdown threshold 3.3 3.9 4.3 v (12) v supply (por) v pwr and v dd power on reset threshold 0.5?0.9 v pwr (uv) v pwr(uv) _up recovery undervoltage threshold 3.4 4.1 4.5 v v dd(fail) v dd supply failure threshold ( for v pwr > v pwr(uv) ) 2.2 2.5 2.8 v notes 9. in extended mode, the functionality is guaranteed but not the electrical parameters. from 4.0 to 6.0 v voltage range, the device is only protected with the thermal shutdown detection. 10. measured with the outputs open. 11. typical value guaranteed per design. 12. output will automatically recover with time limited autoretry to instructed state when v pwr voltage is restored to normal as long as the v pwr degradation level did not go below the undervoltage power-on reset thre shold. this applies to all in ternal device logic that is supplied by v pwr and assumes that the external v dd supply is within specification. free datasheet http:///
analog integrated circuit device data ? 12 freescale semiconductor 10XSC425 outputs hs0 to hs3 r ds_01(on) hs[0,1] output drain-to-source on resistance (i hs = 5.0 a, t a = 25 ? c) ?v pwr = 4.5 v ?v pwr = 6.0 v ?v pwr = 10 v ?v pwr = 13 v ? ? ? ? ? ? ? ? 36 16 10 10 m ? r ds_01(on) hs[0,1] output drain-to-source on resistance (i hs = 5.0 a, t a = 150 ? c) ?v pwr = 4.5 v ?v pwr = 6.0 v ?v pwr = 10 v ?v pwr = 13 v ? ? ? ? ? ? ? ? 62 27 17 17 m ? r sd_01(on) hs[0,1] output source-to-drain on resistance (i hs = -5.0 a, v pwr= -18 v) ?t a = 25 ? c ?t a = 150 ? c ? ? ? ? 15 20 m ? (13) r ds_23(on) hs[2,3] output drain-to-source on resistance (i hs = 5.0 a, t a = 25 ? c) ?v pwr = 4.5 v ?v pwr = 6.0 v ?v pwr = 10 v ?v pwr = 13 v ? ? ? ? ? ? ? ? 90 40 25 25 m ? r ds_23(on) hs[2,3] output drain-to-source on resistance (i hs = 5.0 a, t a = 150 ? c) ?v pwr = 4.5 v ?v pwr = 6.0 v ?v pwr = 10 v ?v pwr = 13 v ? ? ? ? ? ? ? ? 153 68 42.5 42.5 m ? r sd_23(on) hs[2,3] output source-to-drain on resistance (i hs = -5.0 a, v pwr= -18 v) ?t a = 25 ? c ?t a = 150 ? c ? ? ? ? 37.5 50 m ? (13) r short_01 hs[0,1] maximum severe short-circuit impedance detection 28 67 100 m ? (14) r short_23 hs[2,3] maximum severe short-circuit impedance detection 70 160 200 m ? (14) i off hs[0-3] output leakage current in off-state ? in sleep mode ? in normal mode (os_dis = 1 and oloff_dis = 1) ? ? ? ? 5.0 30 ? a notes 13. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr . 14. short-circuit impedance calcul ated from hs[0:3] to gnd pins. value guaranteed per design. table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ??? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 13 10XSC425 outputs hs0 to hs3 (continued) ochi1_0 ochi2_0 oc1_0 oc2_0 oc3_0 oc4_0 oclo4_0 oclo3_0 oclo2_0 oclo1_0 ochi1_1 ochi2_1 oc1_1 oc2_1 oc3_1 oc4_1 oclo4_1 oclo3_1 oclo2_1 oclo1_1 hs[0,1] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) ? 28w bit = 0 ? 28w bit = 1 77.6 46.4 43.6 40.2 31.6 26.2 19.2 12.1 10.3 6.2 38.8 23.2 21.8 18.6 15.8 13.1 4.6 4.6 4.6 2.9 101.6 62 55.6 48.8 40.4 33.2 24.3 15.3 13.1 8.3 50.8 31 27.8 23.8 20.2 16.6 6.3 6.3 6.3 4.1 125.6 77.6 67.6 57.4 49.2 40.2 29.4 18.4 15.9 10.3 62.8 38.8 33.8 29 24.6 20.1 8.0 8.0 8.0 5.3 a c sr0_0 c sr1_0 c sr0_1 c sr1_1 hs[0,1] current sense ratio (6.0 v < hs[0:3] < 20 v, csns < 5.0 v) ? 28w bit = 0 csns_ratio bit = 0 csns_ratio bit = 1 ? 28w bit = 1 csns_ratio bit = 0 csns_ratio bit = 1 ? ? ? ? 1/9900 1/58500 1/4950 1/29250 ? ? ? ? ? (15) c sr0_0_acc hs[0,1] current sense ratio (c sr0 ) accuracy (6.0 v < v hs[0:1] < 20 v) ? with 28w bit = 0 at 25 ? c and 125 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 5.0 a ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a at -40 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 5.0 a ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a -18 -21 -22 -25 -23 -26 -30 -35 ? ? ? ? ? ? ? ? 18 21 22 25 23 26 30 35 % notes 15. current sense ratio = i csns / i hs[0:3] table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ??? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? 14 freescale semiconductor 10XSC425 outputs hs0 to hs3 (continued) c sr0_0_acc (cal) hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 0 ?i hs[0:1] = 5.0 a -5.0 ? 5.0 % (16) ? (c sr0_0 )/ ? (t) hs[0,1] c sr0 current recopy temperature drift (6.0 v < v hs[0:1] < 20 v) ? with 28w bit = 0 ?i hs[0:1] =5.0 a ? ? 0.04 %/ ? c (17) c sr0_1_acc hs[0,1] current sense ratio (c sr0 ) accuracy (6.0 v < v hs[0:1 < 20 v) ? with 28w bit = 1 at 25 ? c and 125 ? c ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a at -40 ? c ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a -22 -25 -30 -35 ? ? ? ? 22 25 30 35 % c sr0_1_acc (cal) hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 1 ?i hs[0:1] = 3.0 a -5.0 ? 5.0 % (16) c sr1_0_acc hs[0,1] current sense ratio (c sr1 ) accuracy (6.0 v < v hs[0:1] < 20 v) ? with 28w bit = 0 at 25 ? c and 125 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 75a at -40 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 75 a -20 -18 -30 -25 ? ? ? ? 20 18 30 25 % c sr1_0_acc (cal) hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 0 ?i hs[0:1] = 12.5 a -5.0 ? 5.0 % (16) c sr1_1_acc hs[0,1] current sense ratio (c sr1 ) accuracy (6.0 v < v hs[0:1] < 20 v) ? with 28w bit = 1 at 25 ? c and 125 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 37.5 a at -40 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 37.5 a -22 -20 -27 -25 ? ? ? ? 22 20 27 25 % c sr1_1_acc (cal) hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 1 ?i hs[0:1] = 12.5 a -5.0 ? 5.0 % (16) notes 16. based on statistical analysis. it is not production tested. 17. based on statistical data: delta (c sr0 )/delta (t) = {(measured i csns at t 1 - measured i csns at t 2 ) / measured i csns at room} / {t 1 -t 2 }. not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ??? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 15 10XSC425 outputs hs0 to hs3 (continued) v cl(csns) current sense clamp voltage ? csns open; i hs[0:3] = 5.0 a with c sr0 ratio v dd +0.25 ? v dd +1.0 v i old(off) off openload detection source current 30 ? 100 ? a (18) v old(thres) off openload fault detection voltage threshold 2.0 3.0 4.0 v i old(on_led) on openload fault detection cu rrent threshold with led (v hs[0:3] = v pwr -0.75 v 2.5 5.0 10 ma i old(on) on openload fault detection current threshold ? hs[0,1] ? hs[2,3] 80 55 360 165 660 330 ma v osd(thres) output short to v pwr detection voltage threshold ? output programmed off v pwr -1.2 v pwr -0.8 v pwr -0.4 v v cl output negative clamp voltage ?0.5 a < i hs[0:3] < 5.0 a, output programmed off - 22 ? -16 v t sd output overtemperature shutdown for 4.5 v < v pwr < 28 v 155 175 195 ? c ochi1_1 ochi2_1 oc1_1 oc2_1 oc3_1 oc4_1 oclo4_1 oclo3_1 oclo2_1 oclo1_1 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 38.8 23.2 21.8 17.3 14.7 12.2 9.2 5.8 4.6 2.9 50.8 31 27.3 22.9 19.2 15.8 11.9 7.6 6.3 4.1 62.8 38.8 32.8 28.4 23.7 19.4 14.5 9.3 8.0 5.3 a c sr0_x c sr1_x hs[2,3] current sense ratio (6.0 v < hs[2:3] < 20 v, csns < 5.0 v) csns_ratio bit = 0 csns_ratio bit = 1 ? ? 1/4670 1/27270 ? ? ? (19) notes 18. output off openload detection current is the current required to flow through the load for the purpose of detecting the exis tence of an openload condition when the specific output is co mmanded off. pull-up current is measured for v hs = v old(thres) 19. current sense ratio = i csns / i hs[0:3] table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ??? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? 16 freescale semiconductor 10XSC425 outputs hs0 to hs3 (continued) c sr0_x_acc hs[2,3] current sense ratio (c sr0 ) accuracy (6.0 v < v hs[2:3] < 20 v) ? with 28w bit = x at 25 ? c and 125 ? c ?i hs[2:3] = 6.25 a ?i hs[2:3] = 2.5 a ?i hs[2:3] = 1.5 a ?i hs[2:3] = 0.75 a at -40 ? c ?i hs[2:3] = 6.25 a ?i hs[2:3] = 2.5 a ?i hs[2:3] = 1.5 a ?i hs[2:3] = 0.75 a -18 -21 -22 -25 -23 -26 -30 -35 ? ? ? ? ? ? ? ? 18 21 22 25 23 26 30 35 % c sr0_x_acc (cal) hs[2,3] current recopy accuracy with one calibration point ? (6.0 v < v hs[2:3] < 20 v) ?i hs[2:3] = 2.5 a -5.0 ? 5.0 % (20) ? (c sr0_x )/ ? (t) hs[2,3] c sr0 current recopy temperature drift (6.0 v < v hs[2:3] < 20 v) with 28w bit = 0 ?i hs[2:3] = 2.5 a ? ? 0.04 %/ ? c (20) c sr1_x_acc hs[2,3] current sense ratio (c sr1 ) accuracy (6.0 v < v hs[2:3] < 20 v) at 25 ? c and 125 ? c ?i hs[2:3] = 6.25 a ?i hs[2:3] = 18.75 a at -40 ? c ?i hs[2:3] = 6.25 a ?i hs[2:3] = 18.75 a -22 -25 -25 -27 ? ? ? ? +22 +25 +25 +27 % c sr1_x_acc (cal) hs[2,3] current recopy accuracy with one calibration point ? (6.0 v < v hs[2:3] < 20 v) ?i hs[2:3] = 6.2 a -5.0 ? 5.0 % (20) control interface v ih input logic high-voltage 2.0 ? v dd +0.3 v (21) v il input logic low-voltage -0.3 ? 0.8 v (21) i dwn input logic pull-down current (sclk, si) 5.0 ? 20 ? a (22) i up input logic pull-up current (csb) 5.0 ? 20 ? a (23) c so so, fsb tri-state capacitance ? ? 20 pf (24) notes 20. based on statistical analysis. it is not production tested. 21. upper and lower logic threshold voltage range applies to si, csb, sclk, rstb, in[0:3], and wake input signals. the wake and rstb signals may be supplied by a derived voltage referenced to v pwr . 22. pull-down current is with v si > 1.0 v and v sclk > 1.0 v. 23. pull-up current is with v csb < 2.0 v. csb has an active internal pull-up to v dd . 24. input capacitance of si, csb, sclk, rstb, in[0:3], and wake. this parameter is guaranteed by process monitoring but is not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ??? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 17 10XSC425 control interface (continued) r dwn input logic pull-down resistor (rstb, wake and in[0:3]) 125 250 500 k ? c in input capacitance ? 4.0 12 pf (26) v cl(wake) wake input clamp voltage ?i cl(wake) < 2.5 ma 18 25 32 v (25) v f(wake) wake input forward voltage ?i cl(wake) = -2.5 ma - 2.0 ? - 0.3 v v soh so high state output voltage ?i oh = 1.0 ma v dd -0.4 ? ? v v sol so and fsb low state output voltage ?i ol = -1.0 ma ? ? 0.4 v i so(leak) so, csns and fsb tri-state leakage current ? csb = v ih and 0.0 v < v so < v dd , or fsb = 5.5 v, or csns = 0.0 v - 2.0 0 2.0 ? a rfs fsi external pull-down resistance watchdog disabled watchdog enabled ? 10 0 infinite 1.0 ? k ? (27) notes 25. the current must be limited by a series resistance when using voltages > 7.0 v. 26. input capacitance of si, csb, sclk, rstb, in[0:3], and wake. this parameter is guaranteed by process monitoring but is not production tested. 27. in fail-safe, hs[0:3] depends respectively on on [0:3]. fsi has an active internal pull-up to v reg ? 3.0 v. table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ??? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? 18 freescale semiconductor 10XSC425 4.3 dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power output timing hs0 to hs3 sr r00 output rising medium slew rate (medium speed slew rate / sr[1:0] = 00) 300 650 1200 mv/ ? s sr f00 output falling medium slew rate (medium speed slew rate / sr[1:0] = 00) 300 720 1200 mv/ ? s ds r_00 driver output matching slew rate (srr /srf) ?pwr = 14 v at 25 c and for medium speed slew rate ? (sr[1:0] = 00) v 0.8 0.9 1.2 sr r01 output rising low slew rate (medium speed slew rate / sr[1:0] = 01) 150 330 600 mv/ ? s sr f01 output falling low slew rate (medium speed slew rate / sr[1:0] = 01) 150 370 600 mv/ ? s sr r10 output rising fast slew rate (medium speed slew rate / sr[1:0] = 10) 600 1250 2400 mv/ ? s sr f10 output falling fast slew rate (medium speed slew rate / sr[1:0] = 10) 600 1450 2400 mv/ ? s t dly_on hs[0:1] outputs turn-on delay times ? vpwr = 14 for medium speed slew rate (sr[1:0] = 00) v 40 64 100 ? s (28) , (29) t dly_off hs[0:1] outputs turn-off delay times ? vpwr = 14 for medium speed slew rate (sr[1:0] = 00) v 10 32 60 ? s (28) , (29) ?? t rf hs[0:1] driver output matching time (t dly(on) - t dly(off) ) ? vpwr = 14 v, f pwm = 240 hz, pwm duty cycle = 50%, at 25 c for medium speed slew rate (sr[1:0] = 00) 10 32 60 ? s (28) , (29) sr r00 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 200 470 800 mv/ ? s sr f00 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 200 570 800 mv/ ? s ds r_00 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 0.6 0.8 1.0 sr r01 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 100 230 400 mv/ ? s sr f01 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 100 300 400 mv/ ? s notes 28. turn on delay time measured fr om rising edge of any signal (in[0 : 3] and csb) that would turn the output on to v hs[0 : 3] = v pwr / 2 with r l = 5.0 ? resistive load. 29. turn off delay time measured from falling edge of any signal (in[0 : 3] and csb) that would turn the output off to v hs[0 : 3] = v pwr / 2 with r l = 5.0 ? resistive load. free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 19 10XSC425 power output timing hs0 to hs3 (continued) sr r10 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 400 900 1600 mv/ ? s sr f10 hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 400 1140 1600 mv/ ? s t dly_on hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 40 87 160 ? s t dly_off hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 15 36 65 ? s ?? t rf hs[2,3] output overcurrent detection levels (6.0 v < v hs[0:3] < 20 v) 10 51 110 ? s t fault fault detection blanking time 1.0 5.0 20 ? s (30) t detect output shutdown delay time ? 7.0 30 ? s (31) t cnsval csns valid time ? 70 100 ? s (32) t wdto watchdog timeout 217 310 400 ms (33) t old(led) on openload fault cyclic detection time with led 105 150 195 ms notes 30. time necessary to report the fault to fsb pin. 31. time necessary to switch-off the output in case of ot, or oc, or sc, or uv fault detection (from negative edge of fsb pin to hs voltage = 50% of v pwr . 32. time necessary for csns to be within 5.0% of the targeted value (from hs voltage = 50% of v pwr to 5.0% of the targeted csns value). 33. for fsi open, the watchdog timeout delay measured from the ri sing edge of rst, to hs[0,2] output state depend on the corresp onding input command. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? 20 freescale semiconductor 10XSC425 power output timing hs0 to hs3 (continued) t oc1_00 t oc2_00 t oc3_00 t oc4_00 t oc5_00 t oc6_00 t oc7_00 t oc1_01 t oc2_01 t oc3_01 t oc4_01 t oc5_01 t oc6_01 t oc7_01 t oc1_10 t oc2_10 t oc3_10 t oc4_10 t oc5_10 t oc6_10 t oc7_10 t oc1_11 t oc2_11 t oc3_11 t oc4_11 t oc5_11 t oc6_11 t oc7_11 hs[0,1] output overcurrent time step for 28w bit = 0 ? oc[1:0] = 00 (slow by default) ? oc[1:0] = 01 (fast) ? oc[1:0] = 10 (medium) ? oc[1:0] = 11 (very slow) 4.40 1.62 2.10 2.88 4.58 10.16 73.2 1.10 0.40 0.52 0.72 1.14 2.54 18.2 2.20 0.81 1.05 1.44 2.29 5.08 36.6 8.8 3.2 4.2 5.7 9.1 20.3 146.4 6.30 2.32 3.00 4.12 6.56 14.52 104.6 1.57 0.58 0.75 1.03 1.64 3.63 26.1 3.15 1.16 1.50 2.06 3.28 7.26 52.3 12.6 4.6 6.0 8.2 13.1 29.0 209.2 8.02 3.00 3.90 5.36 8.54 18.88 134.0 2.00 0.75 0.98 1.34 2.13 4.72 34.0 4.01 1.50 1.95 2.68 4.27 9.44 68.0 16.4 21.4 7.8 10.7 17.0 37.7 272.0 ms table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 21 10XSC425 power output timing hs0 to hs3 (continued) t oc1_00 t oc2_00 t oc3_00 t oc4_00 t oc5_00 t oc6_00 t oc7_00 t oc1_01 t oc2_01 t oc3_01 t oc4_01 t oc5_01 t oc6_01 t oc7_01 t oc1_10 t oc2_10 t oc3_10 t oc4_10 t oc5_10 t oc6_10 t oc7_10 t oc1_11 t oc2_11 t oc3_11 t oc4_11 t oc5_11 t oc6_11 t oc7_11 hs[0,1] output overcurrent time step for 28w bit = 1 hs[2,3] output overcurrent time step ? oc[1:0] = 00 (slow by default) ? oc[1:0] = 01 (fast) ? oc[1:0] = 10 (medium) ? oc[1:0] = 11 (very slow) 3.4 1.1 1.4 2.0 3.4 8.5 62.4 0.86 0.28 0.36 0.51 0.78 2.14 20.2 1.7 0.5 0.7 1.0 1.7 4.2 31.2 6.8 2.2 2.9 4.0 6.8 17.0 124.8 4.9 1.6 2.1 2.9 4.9 12.2 89.2 1.24 0.40 0.52 0.74 1.12 3.06 22.2 2.5 0.8 1.0 1.5 2.5 6.1 44.6 9.8 3.2 4.2 5.8 9.8 24.4 178.4 6.4 2.1 2.8 3.8 6.4 15.9 116.0 1.61 0.52 0.68 0.96 1.46 3.98 28.9 3.3 1.0 1.3 2.0 3.3 6.0 58.0 12.8 16.7 5.5 7.6 12.8 31.8 232.0 ms table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? 22 freescale semiconductor 10XSC425 power output timing hs0 to hs3 (continued) t bc1_00 t bc2_00 t bc3_00 t bc4_00 t bc5_00 t bc6_00 t bc1_01 t bc2_01 t bc3_01 t bc4_01 t bc5_01 t bc6_01 t bc1_10 t bc2_10 t bc3_10 t bc4_10 t bc5_10 t bc6_10 t bc1_00 t bc2_00 t bc3_00 t bc4_00 t bc5_00 t bc6_00 t bc1_01 t bc2_01 t bc3_01 t bc4_01 t bc5_01 t bc6_01 t bc1_10 t bc2_10 t bc3_10 t bc4_10 t bc5_10 t bc6_10 hs[0,1] bulb cooling time step for 28w bit = 0 ? cb[1:0] = 00 or 11 (medium) ? cb[1:0] = 01 (fast) ? cb[1:0] = 10 (slow) hs[0,1] for 28w bit = 1 or for hs2-hs3 ? cb[1:0] = 00 or 11 (medium) ? cb[1:0] = 01 (fast) ? cb[1:0] = 10 (slow) 242 126 140 158 181 211 121 63 70 79 90 105 484 252 280 316 362 422 291 156 178 208 251 314 146 78 88 101 126 226 583 312 357 417 501 628 347 181 200 226 259 302 173 90 100 113 129 151 694 362 400 452 518 604 417 224 255 298 359 449 209 112 127 145 180 324 834 448 510 596 717 898 452 236 260 294 337 393 226 118 130 147 169 197 1904 472 520 588 674 786 542 292 332 388 467 584 272 146 166 189 234 422 1085 582 665 775 933 1170 ms table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 23 10XSC425 pwm module timing f in0 input pwm clock range on in0 7.68 ? 30.72 khz f in0(low) input pwm clock low frequency detection range on in0 1.0 2.0 4.0 khz (35) f in0(high) input pwm clock high frequency detection range on in0 100 ? 400 khz (35) f pwm output pwm frequency range using external clock on in0 31.25 ? 781 hz a fpwm(cal) output pwm frequency accuracy using calibrated oscillator -10 ? +10 % f pwm(0) default output pwm frequency using internal oscillator 84 120 156 hz t csb(min) csb calibration low minimum time detection range 14 20 26 ? s t csb(max) csb calibration low maximum tine detection range 140 200 260 ? s r pwm _1k output pwm duty cycle range for f pwm = 1.0 khz for high speed slew rate 10 ? 94 % (35) r pwm _400 output pwm duty cycle range for f pwm = 400 hz 6.0 ? 98 % (35) r pwm _200 output pwm duty cycle range for f pwm = 200 hz 5.0 ? 98 % (35) input timing t in direct input toggle timeout 175 250 325 ms autoretry timing t auto autoretry period 105 150 195 ms temperature on the gnd flag t otwar thermal prewarning detection 110 125 140 c (36) t feed analog temperature feedback at t a = 25 c with r csns = 2.5 k ? 1.15 1.20 1.25 v dt feed analog temperature feedback derating with r csns = 2.5 k ? -3.5 -3.7 -3.9 mv/c (37) notes 34. clock fail detector available fo r pwm_en bit is set to logic [1] and clock_sel is set to logic [0]. 35. the pwm ratio is measured at v hs = 50% of v pwr and for the default sr value. it is possible to put the device fully on (pwm duty cycle 100%) and fully off (duty cycle 0%). for values outside this r ange, a calibration is needed between the pwm duty cycle programm ing and the pwm on the output with r l = 5.0 ? resistive load. 36. typical value guaranteed per design. 37. value guaranteed per statistical analysis. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? 24 freescale semiconductor 10XSC425 spi interface characteristics (38) f spi maximum frequency of spi operation ? ? 8.0 mhz t wrstb required low state duration for rstb 10 ? ? ? s (39) t csb rising edge of csb to falling edge of csb (required setup time) ? ? 1.0 ? s (40) t enbl rising edge of rstb to falling edge of csb (required setup time) ? ? 5.0 ? s (40) t lead falling edge of csb to rising edge of sclk (required setup time) ? ? 500 ns (40) t wsclkh required high state duration of sclk (required setup time) ? ? 50 ns (40) t wsclkl required low state duration of sclk (required setup time) ? ? 50 ns (40) t lag falling edge of sclk to rising edge of csb (required setup time) ? ? 60 ns (40) t si (su) si to falling edge of sclk (required setup time) ? ? 37 ns (41) t si (hold) falling edge of sclk to si (required setup time) ? ? 49 ns (41) t rso so rise time ?c l = 80 pf ? ? 13 ns t fso so fall time ?c l = 80 pf ? ? 13 ns t rsi si, csb, sclk, incoming signal rise time ? ? 13 ns (41) t fsi si, csb, sclk, incoming signal fall time ? ? 13 ns (41) t so(en) time from falling edge of csb to so low-impedance ? ? 60 ns (42) t so(dis) time from rising edge of csb to so high-impedance ? ? 60 ns (43) notes 38. parameters guaranteed by design. 39. rstb low duration measured with outputs enabled and going to off or disabled condition. 40. maximum setup time required for the 10XSC425 is the minimum guaranteed time needed from the microcontroller. 41. rise and fall time of incoming si, csb, and sclk signals sugges ted for design consideration to prevent the occurrence of dou ble pulsing. 42. time required for output status data to be available for use at so. 1.0 k ?? on pull-up on csb. 43. time required for output status data to be terminated at so. 1.0 k ?? on pull-up on csb. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 25 10XSC425 4.4 timing diagrams figure 4. output slew rate and time delays figure 5. overcurrent shutdown protection v pwr v hs[0:3] t dly(on) t dly(off) low logic level 70% v pwr 30% v pwr sr f sr r 50%v pwr r pwm csb high logic level v hs[0:3] time time time low logic level in[0:3] high logic level time or i och1 t oc5 t oc4 t oc2 t oc1 time load current i och2 i oc1 i oc3 i oc4 i oclo4 i oclo3 i oc2 t oc3 t oc6 t oc7 i oclo2 i oclo1 free datasheet http:///
analog integrated circuit device data ? 26 freescale semiconductor 10XSC425 figure 6. bulb cooling management figure 7. input timing switch ing characteristics i och1 t b c5 t b c4 t b c2 t b c1 previous off duration (toff) i och2 i oc1 i oc3 i oc4 i oclo4 i oclo3 i oc2 t b c3 t b c6 i oclo2 i oclo1 si rstb csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.2 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl rstb sclk si csb 10% v dd t wrstb t enbl 10% v dd t lead t wsclkh t rsi 90% v dd 10% v dd 90% v dd 10% v dd t si(su) t wsclkl t si(hold) t fsi 90% v dd t csb t lag vih vih vil vil vih vil vih vih free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 27 10XSC425 figure 8. sclk waveform and valid so data delay time so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 90% v dd sclk so so voh vol voh vol voh vol 10% v dd 10% v dd 90% v dd t rso t fso 10% v dd t so(en) t so(dis) low to high high to low t valid 90% v dd free datasheet http:///
analog integrated circuit device data ? 28 freescale semiconductor 10XSC425 5 functional description 5.1 introduction the 10XSC425 is one in a family of devices designed for low-voltage lighting app lications. its four low r ds(on) mosfets (dual 10 m ? , dual 25 m ? ) can control four separate 55 w / 28 w bulbs and/or xenon modules. programming, control, and diagnostics are accomplished using a 16 -bit spi interface. its output with selectable slew rate improves electromagnetic compat ibility (emc) behavior. additionally, each output has its own parallel input or spi control for pulse-width modulation (pwm) control if desired. the 10XSC425 al lows the user to program via the spi the fault current trip levels and duration of acceptable lamp inrush. the device has fa il-safe mode to provide fail-safe functionality of the outputs in case of mcu damaged. 5.2 functional pin description 5.2.1 output current monitoring (csns) the current sense pin provides a curr ent proportional to the designated hs0 : hs3 output or a voltage proportional to the temperature on the gnd flag. th at current is fed into a ground-referenced resistor (3.3 k ? , typical) and its voltage is monitored by an mcu's a/d. the output type is selected via t he spi. this pin can be tri-stated through the spi. 5.2.2 direct inputs (in0, in1, in2, in3) each in input wakes the device. the in0 : in3 high side input pins are also used to directly control hs0 : hs3 high side output pins. if the outputs are controlled by the pwm module, the external pwm clock is applied to the in0 pin. these pins are to be driven with cmos levels, and they have a passive internal pull-down, r dwn . 5.2.3 fault status (fsb) this pin is an open drain configured output requiring an external pull-up resistor to v dd for fault reporting. if a device fault condition is detected, this pi n is active low. specific device diagnosti cs and faults are reported via the spi so pin. 5.2.4 wake the wake input wakes the device. an inter nal clamp protects this pin from high damaging voltages with a series resistor (10 k ?? typ). this input has a passive internal pull-down, r dwn . 5.2.5 reset (rstb) the reset input wakes the device. this is us ed to initialize the device configuration and fault registers, as well as drive the device into a low-current sleep mode. the pin also starts the wa tchdog timer when transitioning from logic [0] to logic [1]. this pin has a passive internal pull-down, r dwn . 5.2.6 chip select (csb) the csb pin enables communication with the master micr ocontroller (mcu). when this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the mcu. the 10XSC425 la tches in data from the input shift registers to the addressed registers on the rising edge of csb . the device transfers status information from the power output to the shift register on the falling edge of csb . the so output driver is enabled when csb is a logic [0]. csb should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. csb has an active internal pull-up from v dd , i up . free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 29 10XSC425 5.2.7 serial clock (sclk) the sclk pin clocks the internal shift registers of the 10XSC425 de vice. the serial input (si) pi n accepts data into the input shift register on the falling edge of the sclk signal, while the serial output (so) pin shifts data information out of the so line dr iver on the rising edge of the sclk signal. it is importa nt the sclk pin be in a logic low state whenever csb makes any transition. for this reason, it is recommended the sclk pin be in a logic [0] whenever the device is not accessed ( csb logic [1] state). sclk has an active internal pull-down. when csb is logic [1], signals at the sclk and si pins are ignored and so is tri-stated (high- impedance) (see figure 10 , page 31 ). sclk input has an active internal pull-down, i dwn . 5.2.8 serial input (si) this is a serial interface (si) command data input pin. each si bit is read on the falling edge of sclk. a 16-bit stream of ser ial data is required on the si pin, st arting with d15 (msb) to d0 (lsb). the internal registers of the 10XSC425 are configured and controlled using a 5-bit addressing scheme described in table 10 . register addressing and configuration are described in table 11 . si input has an active internal pull-down, i dwn . 5.2.9 digital drain voltage (vdd) this pin is an external voltage input pin used to supply power to the spi circuit. in the event v dd is lost (v dd failure), the device goes to fail-safe mode. 5.2.10 ground (gnd) these pins are the ground for the device. 5.2.11 positive power supply (vpwr) this pin connects to the positive power supply and is the source of operational power for the device. the vpwr contact is the backside surfac e mount tab of the package. 5.2.12 serial output (so) the so data pin is a tri-stateable output from the shift register. the so pin re mains in a high-impedance state until the csb pin is put into a logic [0] state. the so data is capable of reporting the status of the output, the device conf iguration, the state of the key inputs, etc. the so pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. so reporting descriptions are provided in table 23 . 5.2.13 high side outputs (hs3, hs1, hs0, hs2) protected 10 m ? and 25 m ? high side power outputs to the load. 5.2.14 fail-safe input (fsi) this pin incorporates an active internal pul l-up current source from internal supply (v reg ). this enables the watchdog timeout feature. when the fsi pin is opened, t he watchdog circuit is enabled. after a watc hdog timeout occurs, the output states depends on in[0:3]. when the fsi pin is connected to gnd, t he watchdog circuit is disabled. the output states depends on in[0:3] in case of a v dd failure condition. in case a v dd failure detection is activated (vdd_fail_en bit sets to logic [1]). free datasheet http:///
analog integrated circuit device data ? 30 freescale semiconductor 10XSC425 5.3 functional internal block description figure 9. functional block diagram 5.3.1 power supply the 10XSC425 is designed to operate from 4.0 to 28 v on the vpwr pin. characteristics are provided from 6.0 to 20 v for the device. the vpwr pin supplies power to internal regulator, anal og, and logic circuit blocks. the vdd supply is used for serial peripheral interface (spi) communication in order to configure and diagnose the device. this ic architecture provides a low quiescent current sleep mode. applying v pwr and v dd to the device will place the device in the normal mode. the device will transit to fail-safe mode during failures on the spi or/and on vdd voltage. 5.3.2 high side switches (hs0?hs3) these pins are the high side outputs controlling la mps located for the front of vehicle, such as 65 w/55 w bulbs and xenon-hid modules. those n-channel mosfets with 10 m ? and 25 m ? r ds(on) are self-protected and present extended diagnostics in order to detect bulb outage and short-circui t fault condition. the hs output is active ly clamped during turn off of inductive l oads and inductive battery line. when driving dc motor or solenoid l oads demanding multiple switching, an external recirculation device must be used to maintain the device in its safe operating area. 5.3.3 mcu interface and output control in normal mode, each bulb is controlled dire ctly from the mcu through the spi. a pulse -width modulation control module allows improvement of lamp lifetime with bulb power r egulation (pwm frequency range of 100 to 400 hz) and addressing the dimming application (day running light). an analog f eedback output provides a cu rrent proportional to the lo ad current or the temperatu re of the board. the spi is used to configur e and to read the diagnostic st atus (faults) of high side outputs. the reported fault conditions are: openload, short-circuit to battery, short-circuit to ground (overcu rrent and severe short-circuit), thermal shutdown, and under/overvoltage . owing to accurate and configurable over current detection circuitry and wire-harness optimization, the vehicle is lighter. in fail-safe mode, each lamp is controlled with dedicated para llel input pins. the device is configured in default mode. power supply 10XSC425 - functiona l block diagram parallel control inputs mcu interface & output control spi interface self-protected supply mcu interface & output control self-protected high side switches pwm controller high side switches hs0-hs3 mcu interface free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 31 10XSC425 6 functional device operation 6.1 spi protocol description the spi interface has a full duplex, three- wire synchronous data transfer with four i/o lines associated with it: serial input (si), serial output (so), serial clo ck (sclk), and chip select ( csb ). the si / so pins of the 10XSC425 follow a first-in first-out (d15 to d0) protocol, with both input and output words transferring the most significant bit (msb) first. all inputs are compatible with 5.0 or 3.3 v cmos logic levels. figure 10. single 16-bit word spi communication 6.2 operational modes the 10XSC425 has four operating modes: sleep, normal, fail-safe and fault. table 6 and figure 12 summarize details contained in succeeding paragraphs. the figure 11 describes an internal signal called in_on[x] depending on in[x] input. figure 11. in_on[x] internal signal the 10XSC425 transits to operating modes according to the following signals: ? wake-up = rstb or wake or in_on[0] or in_on[ 1] or in_on[2] or in_on[3], ? fail = (v dd failure and vdd_fail_en) or (watchdog ti meout and fsi input not shorted to ground), ? fault = oc[0:3] or ot[0:3] or sc[0:3] or uv or (ov and ov_dis ). cs csb si sclk so d15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d14 d13 d12 d11 d10 od12 d0 od13 od14 od15 od6 od7 od8 od9 od10 od11 od1 od2 od3 od4 od5 1. rstb is in a logic h state during the above operation. 2. do, d1, d2, ... , and d15 relate to the most recent ordered entry of program data into the lux ic 3. od0, od1, od2, ..., and od15 relate to the first 16 bits of ordered fault and status data out of the lux ic notes: od0 csb device. device. 1. rstb is a logic [1] state during the above operation. 2. d15 : d0 relate to the most recent ordered entry of data into the device. 3. od15 : od0 relate to the first 16 bits of order ed fault and status data out of the device. notes in_on[x] in[x] t in free datasheet http:///
analog integrated circuit device data ? 32 freescale semiconductor 10XSC425 figure 12. operating modes 6.2.1 sleep mode the 10XSC425 is in sleep mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 0, ? fail = x, ?fault = x. this is the default mode of the device after first applying battery voltage (v pwr ) prior to any i/o transitions. this is also the state of the device when the wake and rstb and in_on[0:3] are logic [0]. in the sleep mode, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. in addition, all spi-configurable features of the device are as if set to logic [0]. table 6. 10XSC425 operating modes mode wake-up fail fault comments sleep 0 x x device is in sleep mode. all outputs are off. normal 1 0 0 device is currently in normal mode. watchdog is active if enabled. fail-safe 1 1 0 device is currently in fail-safe mode due to watchdog timeout or v dd failure conditions. the output states are defined with the rfs resistor connected to fsi. fault 1 x 1 device is currently in fault mode. the faulted output(s) is (are) off. the safe autoretry circuitry is active to turn-on again the output(s). x = don?t care. sleep (fail = 0) and (wake-up = 1) and (fault = 0) (wake-up = 0) fail-safe normal (wake-up = 0) (fail = 1) and (wake-up = 1) and (fault = 0) (fail = 0) and (wake-up = 1) and (fault = 0) (wake-up = 1) and (fail = 1) and ? (fault = 0) fault (wake-up = 0) (wake-up = 1) and (fault = 1) (fail = 0) and (wake-up = 1) and (fault = 1) (fail = 1) and ? (wake-up 0 = 1) and (fault = 1) (fail = 0) and (wake-up = 1) and (fault = 0) (fail = 1) and (wake-up = 1) and (fault = 0) free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 33 10XSC425 6.2.2 normal mode the 10XSC425 is in normal mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 1, ? fail = 0, ?fault = 0. in this mode, the nm bit is set to lfault_contrologic [1] and the outputs hs[0:3] are under control, as defined by hson signal: hson[x] = ( ( (in[x] and dir_dis [x]) or on bit[x] ) and pwm_en ) or (on bit [x] and duty_cycle[x] and pwm_en). in this mode and also in fail-safe, the fault condition rese t depends on fault_control signal, as defined by the following: fault_control[x] = ( (in_on[x] and dir_dis [x]) and pwm_en ) or (on bit [x]). 6.2.2.1 programmable pwm module the outputs hs[0:3] are controlled by th e programmable pwm module if pwm_en and the on bits are set to logic [1]. the clock frequency from in0 input pin or from internal clock is the factor 2 7 (128) of the output pwm frequency (clock_sel bit). the outputs hs[0:3] can be controlled in the range of 5.0 to 98% with a resolution of seven bits of duty cycle ( table 7 ). the state of other in pin is ignored. the timing includes seven programmable pwm switching delay (n umber of pwm clock rising edges) to improve overall emc behavior of the light module ( table 8 ). the clock frequency from in0 is permanently monitored in order to report a clock failure in case the frequency is out of the specified frequency range (from f in0(low) to f in0(high) ). in case of a clock fa ilure, no pwm feature is provided, the on bit defines the outputs state and the clock_fail bit reports [1]. table 7. output pwm resolution on bit duty cycle output state 0 x off 1 0000000 pwm (1/128 duty cycle) 1 0000001 pwm (2/128 duty cycle) 1 0000010 pwm (3/128 duty cycle) 1 n pwm ((n+1)/128 duty cycle) 1 1111111 fully on table 8. output pwm switching delay delay bits output delay 000 no delay 001 16 pwm clock periods 010 32 pwm clock periods 011 48 pwm clock periods 100 64 pwm clock periods 101 80 pwm clock periods 110 96 pwm clock periods 111 112 pwm clock periods free datasheet http:///
analog integrated circuit device data ? 34 freescale semiconductor 10XSC425 6.2.2.2 calibratable internal clock the internal clock can vary as much as ? 30%, corresponding to a typical f pwm(0) output switching period. using the existing spi inputs and the precis ion timing reference already available to the mcu, the 10XSC425 allows clock period setting within ? 10% accuracy. calibrating the internal clock is initiated by defined word to calr register. the calibration pulse is provided by the mcu. the pulse is sent on the csb pin after the spi word is launched. at the moment, the csb pin transitions from a logic [1] to [0], until from a logic [0] to [1], determ ine the period of the internal clock with a multiplicative factor of 128. in case a negative csb pulse is outside a predefined time range (from t csb(min) to t csb(max) ), the calibration event will be ignored and the internal clock will be unaltered, or reset to the default value (f pwm(0) ), if this was not calibrated before. the calibratable clock is used instead of the clock from the in0 input, when clock_sel is set to [1]. 6.2.3 fail-safe mode the 10XSC425 is in fail-safe mode when: ?v pwr is within the normal voltage range, ? wake-up = 1, ? fail = 1, ?fault = 0. 6.2.4 watchdog if the fsi input is not grounded, the wa tchdog timeout detection is active wh en either the wake, or in_on[0:3], or rstb input pin transitions from logic [0] to logic [1]. the wake input is capable of bein g pulled up to v pwr with a series of limiting resistance limiting the internal clamp current according to the specification. the watchdog timeout is a multip le of an internal oscillator . as long as the wd bit (d15) of an incoming spi message is toggled within the minimum watchdog timeout period (w dto), the device will operate normally. 6.2.4.1 fail-safe conditions if an internal watchdog timeout occurs before the wd bit for fsi open ( table 9 ) or in case of a v dd failure condition (v dd < v dd(fail) ) for vdd_fail_en bit is set to logic [1], the device will revert to a fail-safe mode until the wd bit is written to a logic [1 ] (see fail-safe to normal mode transition paragraph) and v dd is within the normal voltage range. during the fail-safe mode, the outputs will depend on the correspon ding input. the spi register content is reset to their defau lt value (except por bit) and fault protection s are fully operational. the fail-safe mode can be detected by monitoring the nm bit is set to [0]. table 9. spi watchdog activation typical rfsi ( ? ) watchdog 0 (shorted to ground) disabled (open) enable csb si calr si command ignored internal clock duration free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 35 10XSC425 6.2.5 normal and fail-sa fe mode transitions 6.2.5.1 transition fail-safe to normal mode to leave the fail-safe mode, v dd must be in nominal voltage and the microcont roller has to send a spi command with the wdin bit set to logic [1]; the other bits are not considered. the previous latched faults ar e reset by the transition into normal mo de (autoretry included). moreover, the device can be brought out of the fail-safe mode d ue to a watchdog timeout issue, by forcing the fsi pin to logic [0]. 6.2.5.2 transition normal to fail-safe mode to leave the normal mode, a fail-safe condit ion must occurred (fail=1). the previous la tched faults are reset by the transition into fail-safe mode (autoretry included). 6.2.6 fault mode the 10XSC425 is in fault mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 1, ? fail = x, ?fault=1. this device indicates the faults below as they occur by driving the fsb pin to logic [0] for rstb input is pulled up: ? overtemperature fault, ? overcurrent fault, ? severe short-circuit fault, ? output(s) shorted to vpwr fault in off state, ? openload fault in off state, ? overvoltage fault (enabled by default), ? undervoltage fault. the fsb pin will automatically return to logic [1] when the fault condition is removed, exce pt for overcurrent, severe short-circuit, overtemperature, and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled). fault information is retained in the spi fault register and is available (and reset) via the so pin during the first valid spi communication. the openload fault in on state is only reported through spi register without effect on the corresponding output state (hs[x]) and the fsb pin. 6.2.7 start-up sequence the 10XSC425 enters in normal mode after start-up if following sequence is provided: ? vpwr and vdd power supplies must be above their undervoltage thresholds, ? generate wake-up event (wake-up = 1) from 0 to 1 on rstb. the device switches to normal mode with the spi register content reset (as defined in table 11 and table 23 ). all features of the 10XSC425 will be available after 50 ? s (typical), and all spi registers are set to def ault values (set to logic [0]). ? toggle wd bit from 0 to 1. and, in case of the pwm module is used (pwm_en bit is set to logic [1]) with an external reference clock: ? apply the pwm clock on the in0 input pin after a maximum of 200 ? s (min. 50 ? s). if the correct start-up sequence is not provided, the pwm function is not guaranteed. free datasheet http:///
analog integrated circuit device data ? 36 freescale semiconductor 10XSC425 6.3 protection and diagnostic features 6.3.1 protections 6.3.1.1 overtemperature fault the 10XSC425 incorporates overtemp erature detection and shutdown ci rcuitry for each output structure. two cases need to be considered when th e output temperature is higher than t sd : ? if the output command is on: the correspo nding output is latched off. fsb will be also latched to logic [0]. to delatch the fault and be able to turn the outputs on again, the failure condition must disappear and the autoretry circuitry must be active, or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output), or v supply(por) condition, if v dd = 0. ? if the output command is off: fsb will go to logic [0] till the corresponding output temperature will be below t sd . for both cases, the fault register ot[0:3] bit into the status r egister will be set to [1]. the fault bits will be cleared in t he status register after a spi read command. 6.3.1.2 overcurrent fault the 10XSC425 incorporates output shutdown, to protect each output stru cture against a resistive shor t-circuit condition. this protection is composed by eight predefined current leve ls (time dependent) to fit xenon-hid manners by default or, 55 w or 28 w bulb profiles, selectable separately by xenon bit and 28 w bits (as illustrated figure 14 ). at the first turn-on, the lamp filament is cold and the curre nt will be huge. the fault_control signal transition from logic [0 ] to [1], or an autoretry define this event. in this case, the overcurrent protection will be fitted to inrush current, as shown in figure 5 . this overcurrent protection is programmable: oc[1:0] bits select the overcurrent slope speed and the ochi1 current step can be removed in case the o chi bit is set to [1]. in steady state, the wire harness will be protected by a oclo2 current level by def ault. three other dc overcurrent levels are available: oclo1, or oclo3, or oclo4, based on the state of the oclo[1,0] bits. if the load current level ever reaches the overcurrent detecti on level, the corresponding outpu t will latch the output off and fsb will be also latched to logic [0]. to delatch the fault and be able to turn the corresponding output on again, the failure cond ition must disappear and the autoretry circuitr y must be active, or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output), or v supply(por) condition, if v dd = 0. the spi fault report (oc[0:3] bits) is removed after a read operation. in normal mode using the internal pwm module, the 10XSC425 also incorporates a cooling bulb filament management, if oc_mode and xenon are set to logic [1]. in this case, the first step of multi-step overcurrent protecti on will depend on the previous off duration, as illustrated in figure 6 . the following figure illustrates the current level that will be used in the function to the duration of the prev ious off state (t off ). the slope of the cooling bulb emulator is configurable with ocoffcb[1:0] bits. hson signal over-current thresholds pwm fault_control hson free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 37 10XSC425 6.3.1.3 severe short-circuit fault the 10XSC425 provides output shutdown to pr otect each output, in case of a severe short-circuit during the output switching. if the short-circuit impedance is below r short, the device will latch the output off, fsb w ill go to a logic [0] and the fault register sc[0:3] bit will be set to [1]. to delatch the fault and be able to turn the outputs on again, the failure condition must disap pear, and the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output), or v supply(por) condition if v dd = 0. the spi fault report (sc[0:3] bits) is removed after a read operation. 6.3.1.4 overvoltage fault (enabled by default) by default, the overvoltage protection is enabled. the 10XSC425 shuts down all outputs and fsb will go to a logic [0] during an overvoltage fault condition on the vpwr pin (v pwr > v pwr(ov) ). the outputs remain in the off state until the overvoltage condition is removed (v pwr < v pwr(ov) - v pwr(ovhys) ). when experiencing this fault, the ovf fault bit is set to logic [1] and cleared after either a valid spi read. the overvoltage protection can be disabled through the spi (ov_dis bit is disabled set to logic [1]). the fault register reflec ts any overvoltage condition (v pwr > v pwr(ov) ). this overvoltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. the hs[0:3] outputs are not commanded in r ds(on) above the ov threshold. 6.3.1.5 undervoltage fault the output(s) will latch off at some battery voltage below vpwr (uv) . as long as the v dd level stays within the normal specified range, the internal logic stat es within the device will remain (configuration and reporting). in the case where battery voltage dr ops below the undervoltage threshold (v pwr < v pwr(uv) ), the outputs will turn off, fsb will go to logic [0], and the fault register uv bit will be set to [1]. two cases need to be considered when the battery level recovers (v pwr > v pwr(uv)_up ): ? if the output command is low, fsb will go to a logic [1], bu t the uv bit will remain set to 1 until the next read operation (warning report). ? if the output command is on, fsb will remain at logic [0]. to delat ch the fault and be able to turn the outputs on again, the failure condition must disappear and the autoretry circuitry must be active, or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output), or a v supply(por) condition, if v dd = 0. in extended mode, the output is protect ed by overtemperature shutdown circuitry. all previous latched faults, occurred when v pwr is within the normal voltage range, are guaranteed if v dd is within the operationa l voltage range, or until v supply(por) , if vdd = 0. any new ot fault is det ected (vdd failure included) and reported through spi above vpwr (uv) . the output state is not changed, as long as the vpwr volt age does not drop any lower than 3.5 v (typical). all latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if: ?v dd < v dd(fail) with v pwr in nominal voltage range, ?v dd and v pwr supplies is below the v supply(por) voltage value. over-current thresholds toff depending to toff cooling pwm hson signal fault_control hson depending on toff free datasheet http:///
analog integrated circuit device data ? 38 freescale semiconductor 10XSC425 figure 13. auto-retry state machine 6.3.2 auto-retry the auto-retry circuitry is used to reactiva te the output(s) automatically, in case of an overcurrent, overtemperature, or undervoltage failure conditions to pr ovide a high availability of the load. auto-retry feature is available in fault mo de. it is activated in case of an intern al retry signal is set to a logic [1]: retry[x] = oc[x] or ot[x] or uv. the feature retries to switch-on the output(s) after one auto-retry period (t auto ) with a limitation in term of the number of occurrences (16 for each output). the counte r of retry occurrences is reset in case of fail-safe to normal or normal to fail-sa fe mode transitions. at each auto-retry, the overcurrent detection will be set to default values in order to sustain the inrush cu rrent. figure 13 describes the auto-retry state machine. 6.3.3 diagnostic 6.3.3.1 output shorted to vpwr fault the 10XSC425 incorporates output shorted to vpwr detection circ uitry in the off state. an output shorted to vpwr fault is detected if the output voltage is higher than v osd(thres) and reported as a fault condition when t he output is disabled (off). the output shorted to vpwr fault is latched into the status register after the internal gate voltage is pulled low enough to turn o ff the output. the os[0:3] and ol_off[0:3] fault bits are set in the status register and the fsb pin reports the fault in real tim e. if the output shorted to vpwr fault is removed, the status register will be cleared after reading the register. the open output shorted to vpwr protection can be disabled through the spi (os_dis[0:3] bit). 6.3.3.2 openload faults the 10XSC425 incorporates three dedicated openload detection circ uitries on the output to detect in off and in on states. off on latched off autoretry off autoretry on (sc = 1) (ov = 1) (fault_control = 1 and ov = 0) (fault_control = 0 or ov = 1) (fault_control = 0) (fault_control=0) (fault_control=0) (sc = 1) (retry = 1) => count = count+1 (retry = 1) (count = 16) (after retry period and ov = 0) (openloadoff = 1 or shortvpwr = 1 (openloadoff = 1 or shortvpwr = 1 (openloadoff = 1 or shortvpwr = 1 (openloadon = 1) (openloadon = 1) or ov = 1) or ov = 1) or ov = 1) if hson=1 if hson = 0 if hson=1 free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 39 10XSC425 6.3.3.3 openload detection in off state the off output openload fault is detected when the out put voltage is higher than v old(thres) pulled up with internal current source ( i old(off) ), and reported as a fault condition when the output is disabled (off). t he off output openloa d fault is latched into the status register, or when the internal gate voltage is pulled low enough to turn the output off. the ol_off[0:3] fault bit is set in the status regi ster. if the openload fault is remov ed (fsb output pin goes to high), the status register will be clea red after reading the register. the off output openload protection can be disabl ed through the spi (oloff_dis[0:3] bit). 6.3.3.4 openload detection in on state the on output openload current thresholds can be chosen by the spi to detect a standard bulb or led (olled[0:3] bit set to logic [1]). in the case where the load current drops below the de fined current threshol d, the olon bit is set to logic [1], the output stays on, and fsb is not disturbed. 6.3.3.5 openload detectio n in on state for led openload for leds only (olled[0:3] set to logic [1]) is detected periodically at each t olled (fully-on, d[6:0]=7f) . to detect olled in a fully on state, the output must be on at least t olled. to delatch the diagnosis, the condition should be removed and a spi read operation is needed (ol_on[0:3] bit). the on output openload protection can be disabled th rough the spi (olon_dis[0:3] bit). 6.3.4 analog current recopy and temperature feedbacks the csns pin is an analog output reporting a current proportiona l to the designed output current, or a voltage proportional to the temperature of the gnd flag (p in #14). the routing is spi programmable (t emp_en, csns_en, csns_s [1,0] and csns_ratio_s bits). in case the current recopy is active, the csns output deliver s current only during the on time of the output switch without overshoot. the maximum current is 2.0 ma (typical). the typical value of the exte rnal csns resistor connected to ground is 2.5 k ? . the current recopy is not active in fail-safe mode. 6.3.4.1 temperature prewarning detection in normal mode, the 10XSC425 provides a temperature prewarni ng reported via the spi, in case the temperature of the gnd flag is higher than t otwar . this diagnosis (otw bit set to [1]) is latched in the spi diagr0 register . to delatch, a spi read command is needed. 6.3.5 active clamp on vpwr the device provides an active gate clamp circuit, to limit the maximum transient vpwr voltage at vpwr (clamp) . in case of an overload on an output the corresponding output is turned off, which leads to high voltage at vpwr with an inductive vpwr line. when vpwr voltage exceeds the vpwr (clamp) threshold, the turn-off on the corre sponding output is deactivated and all hs[0:3] outputs are switched on automatically, to demagnetiz e the inductive battery line. for long battery line (> 10 meters, corresponding to 10 h of parasitic inductance) between the battery and the device, the smart high side switch output may be damaged, in cases of short-circ uit due to unexpected behavior of internal active gate clamp circuitry. it is essential not to exceed the maximum rating on the vpwr pin (41 v). 6.3.6 reverse battery on vpwr the output survives t he application of reverse voltage as low as -18 v. under these conditions, the on resistance of the output is two times higher than the typical ohmic value in forward mode . no additional passive components are required except on the v dd current path. free datasheet http:///
analog integrated circuit device data ? 40 freescale semiconductor 10XSC425 6.3.7 ground disconnect protection in the event the 10XSC425 ground is disconnected from load ground, the device protects itself and safely turns off the output, regardless of the state of the output at the time of disconnection (maximum v pwr = 16 v). a 10 k ? resistor needs to be added between the mcu and each digital input pin, to ensure that the device turns off during ground disconnects and to prevent this p in from exceeding maximum ratings. 6.3.8 loss of supply lines 6.3.8.1 loss of v dd if the external v dd supply is disconnected (or not within specification: vdd < vdd (fail) with the vdd_fail_en bit set to a logic [1]), all spi register content is reset. the outputs can still be driven by the direct inputs in[0 : 3] if v pwr is within specified voltage range. the 10XSC425 uses the battery input to power the output mosfet-re lated current sense circuitry, and any othe r internal logic providing fail-safe devi ce operation with no v dd supplied. in this state, the over temperature, overcurrent, severe s hort-circuit, short to vpwr and off openload circuitry, are fully operational wit h default values corresponding to all spi bits. these are set to logic [0]. an unexpected power-on reset ( v supply(por) ) may occur at 4.8 v of v pwr . the extended battery volt age range specified from 4.0 to 28 v is reduced from 5.0 to 28 v. if the battery voltage drops below 5.0 v, the outputs will be turn ed off by the por instead of undervoltage (uv). in this case, the out puts will turn on again once the battery voltage recovers to a nominal voltage. the counter of auto-retry will be also reset. so , it is recommended to command ?off? the outputs when the battery voltage is below 5.0 v. no current is conducted from v pwr to v dd . 6.3.8.2 loss of v pwr if the external v pwr supply is disconnected (or not within specification), the spi configuration, report ing, and daisy chain features are provided for rstb to set to a logic [1] under v dd in nominal conditions. this fault c ondition can be diagnosed with a uv fault in spi statr_s registers. the spi pull-up and pull-down current so urces are not operational. the previous device configuration is maintained. no current is conducted from v dd to v pwr . 6.3.8.3 loss of v pwr and v dd if the external v pwr and v dd supplies are disconnected (or not within specification: (v dd and v pwr ) < v supply(por) ), all spi register contents are reset with default values corresponding to all spi bits set to logic [0] and all latched faults are reset . 6.3.9 emc performances all following tests are performed on a freescale evaluation b oard, in accordance with the typical application schematic. the device is protected, in case of po sitive and negative transients on the v pwr line (per iso 7637-2). the 10XSC425 successfully meets the class 5 of the cispr25 emission standard and 200 v/m or bci 200 ma injection level for immunity tests. 6.4 logic commands and registers 6.4.1 serial input communication spi communication is accomplished using 16-bit messages. a messa ge is transmitted by the m cu starting with the msb d15 and ending with the lsb, d0 ( table 10 ). each incoming command message on the si pin can be interpreted using the following bit assignments: the msb, d15, is the watchdog bit (wdin) . in some cases, output selection is done with bits d14 : d13. the next three bits, d12: d10, are used to select the co mmand register. the remaining nine bits, d8 : d0, are used to configure and control the outputs and their protection features. free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 41 10XSC425 multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. any attempt made to latch in a message that is not 16 bits will be ignored. the 10XSC425 has defined registers, whic h are used to configure the device and to control the state of the outputs. table 11 summarizes the si registers. ? table 10. si message bit assignment bit sig si msg bit message bit description msb d15 watchdog in: toggled to satisfy watchdog requirements. d14 : d13 register address bits used in some cases for output selection ( table 11 ). d12 : d10 register address bits. d9 not used (set to logic [0]). lsb d8:d0 used to configure the inputs, outputs, and the dev ice protection features and so status content. table 11. serial input address and configuration bit map si register si data d15 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 statr_s wdi n x x 0 0 0 0 0 0 0 0 soa4 soa3 soa2 soa1 soa0 pwmr_s wdi n a 1 a 0 00 10 28w_s on_s pwm6_s pwm5_s pwm4_s pwm3_s pwm2_s pwm1_s pwm0_s confr0 _s wdi n a 1 a 0 01 00 0 0 0 dir_dis_ s sr1_s sr0_s delay2_s delay1_ s delay0_ s confr1 _s wdi n a 1 a 0 0110 0 0 retry_ unlimited_ s retry_dis _s os_dis_s olon_dis _s oloff_di s_s olled_e n_s csns_rati o_s ocr_s wdi n a 1 a 0 1000xenon _s bc1_s bc0_s oc1_s oc0_s ochi_s olco1_s olco0_ s oc_mode _s gcr wdi n 0 0 1010vdd_ fail_ en pwm_e n clock_s el temp_en csns_e n csns1 csns0 x ov_dis calr wdi n 0 0 1110 1 0 1 0 1 1 0 1 1 register state after rstb = 0 or v dd(fail) or v supply( por) condition 000xxx0 0 0 0 0 0 0 0 0 0 x = don?t care. ? s = output selection with the bits a 1 a 0 as defined in table 12 . free datasheet http:///
analog integrated circuit device data ? 42 freescale semiconductor 10XSC425 6.4.2 device register addressing the following section describes the possible register add resses (d[14:10]) and their impact on device operation. 6.4.2.1 address xx000 ? status register (statr_s) the statr register is used to read the device status and the va rious configuration register c ontents without disrupting the dev ice operation or the register contents. the regist er bits d[4:0] determine the content of the first sixteen bits of so data. in add ition to the device status, this feature provides the ability to read the content of the pwmr_s, co nfr0_s, confr1_s, ocr_s, gcr and calr registers (refer to the section entitled serial output communication (device status return data) . 6.4.2.2 address a 1 a 0 001? output pwm control re gister (pwmr_s ) the pwmr_s register allows the mcu to control the state of corresponding ou tput through the spi. each output ?s? is independently selected for configurat ion, based on the state of the d14 : d13 bits ( table 12 ). a logic [1] on bit d8 (28w_s) selects the 28 w overcurrent protection profile: the overcurr ent thresholds are divided by 2 and, the inrush and cooling responses are dedicated to 28 w lamps for hs[0,1] outputs. this bit it not taken into account for hs[2,3] outputs. bit d7 sets the output state. a logic [1] enables the corresponding output switch and a logic [0] turns it off (if in input is also pulled down). bits d6:d0 set t he output pwm du ty-cycle to one of 128 levels for pwm_en is se t to logic [1], as shown table 7 . 6.4.2.3 address a 1 a 0 010? output configuration register (confr0_s ) the confr0_s register allows the mcu to configure corresp onding output switching throu gh the spi. each output ?s? is independently selected for configurat ion based on the state of the d14 : d13 bits ( table 12 ). for the selected output, a logic [0] on bit d5 (dir_dis_s) will enable the output for direct control. a logic [1] on bit d5 will disable the output from direct control (in this case, th e output is only controlled by the on bit). d4:d3 bits (sr1_s and sr0_s) are used to select the high, medium , or low speed slew rate for the selected output, the default value [00] corresponds to the medium speed slew rate ( table 13 ). incoming message bits d2 : d0 reflect the desired output that will be delayed of predefined pwm clock rising edges number, as shown table 8 (only available for pwm_en bit is set to logic [1]). table 12. output selection a 1 (d14) a 0 (d13) hs selection 0 0 hs0 (default) 01hs1 10hs2 11hs3 table 13. slew rate speed selection sr1_s (d4) sr0_s (d3) slew rate speed 0 0 medium (default) 01low 1 0 high 11not used free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 43 10XSC425 6.4.2.4 address a 1 a 0 011 ? output configuration register (confr1_s) the confr1_s register allows the mcu to configure corresponding output fault m anagement through the spi. each output ?s? is independently selected for configurat ion, based on the state of the d14 : d13 bits ( table 12 ). a logic [1] on bit d6 (retry_unlimited_s) disables the autoretry counter for the selected output, the default value [1] corresp onds to enable auto-retry feature without time limitation. a logic [1] on bit d5 (retry_dis_s) disables the auto-retry fo r the selected output, the defaul t value [0] corresponds to enabl e this feature. a logic [1] on bit d4 (os_dis_s) disables the output hard shorted to v pwr protection for the selected output, the default value [0] corresponds to enable this feature. a logic [1] on bit d3 (olon_dis_s) disables the on output openload detection for th e selected output, the default value [0] corresponds to enable this feature ( table 14 ). a logic [1] on bit d2 (oloff_dis_s) disables the off output openload detection for the selected output, the default value [0] corresponds to enable this feature. a logic [1] on bit d1 (olled_en_s) enables the on output openload detection for leds for the selected output, the default value [0] corresponds to on output openload detection is set for bulbs ( table 14 ). a logic [1] on bit d0 (csns_ratio_s) selects the high ratio on the csns pin for the corresponding output. the default value [0] is the low ratio ( table 15 ). 6.4.2.4.1 address a 1 a 0 100 ? output overcurrent register (ocr) the ocr_s register allows the mcu to configure corresponding output overcurrent protection th rough the spi. each output ?s? is independently selected for configur ation based on the state of the d14 : d13 bits ( table 12 ). a logic [1] on bit d8 ( xenon_s ) disables enables the xenon 55 w or 28 w bulb overcurrent profile, as described figure 14 . table 14. on openload selection olon_dis_s (d3) olled_en_s (d1) on openload detection 0 0 enable with bulb threshold (default) 0 1 enable with led threshold 1 x disable table 15. current sense ratio selection csns_high_s (d0) current sense ratio 0 crs0 (default) 1 crs1 free datasheet http:///
analog integrated circuit device data ? 44 freescale semiconductor 10XSC425 figure 14. overcurrent profile depending on xenon bit d[7:6] bits allow to mcu to programmable the bulb cooling curve and d[5:4] bits inrush curve for the selected output, as shown table 16 and table 17 . a logic [1] on bit d3 (ochi_s bit) the o chi1 level is replaced by ochi2 during t oc1 , as shown figure 15 . table 16. cooling curve selection bc1_s (d7) bc0_s (d6) profile curves speed 0 0 medium (default) 01 slow 10 fast 1 1 medium table 17. inrush curve selection oc1_s (d5) oc0_s (d4) profile curves speed 0 0 slow (default) 01fast 1 0 medium 1 1 very slow xenon bit set to logic [1]: xenon bit set to logic [0]: i och1 i och2 i oc1 i oc2 i oclo3 i oclo2 i oclo1 i oclo4 t oc1 t oc3 t oc4 t oc5 t oc6 t oc7 time t oc2 t oc1 t oc2 t oc3 t oc4 t oc5 t oc6 t oc7 time i och1 i och2 i oc1 i oc2 i oc3 i oc4 i ocl3 i ocl2 i ocl1 i ocl4 free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 45 10XSC425 figure 15. overcurrent profile with ochi bit set to ?1? the wire harness is protected by one of four possible current levels in steady state, as defined in table 18 . bit d0 (oc_mode_sel) allows to select the overcurrent mode, as described table 19 . address 00101 ? global configuration register (gcr) the gcr register allows the mcu to configure the device through the spi. bit d8 allows the mcu to enable or disable the vdd failure detec tor. a logic [1] on vdd_fail_en bit allows switch of the output s hs[0:3] with pwmr register device in fail-safe mode in case of v dd < v dd(fail). bit d7 allows the mcu to enable or disable the pwm module. a logic [1] on pwm_en bit allows control of the outputs hs[0:3] with pwmr register (the direct input states are ignored). bit d6 (clock_sel) allows to select the clock used as reference by pwm module, as described in the following table 20 . bits d5:d4 allow the mcu to sele ct one of two analog feedbacks on csns output pin, as shown in table 21 . table 18. output steady state selection oclo1 (d2) oclo0 (d1) steady state current 0 0 oclo2 (default) 01 oclo3 10 oclo4 11 oclo1 table 19. overcurrent mode selection oc_mode_s (d0) overcurrent mode 0 only inrush current management (default) 1 inrush current and bulb cooling management table 20. pwm module selection pwm_en (d7) clock_sel (d6) pwm module 0x pwm module disabled (default) 10 pwm module enabled with external clock from in0 11 pwm module enabled with internal calibrated clock i och1 i och2 i oc1 i oc2 i oc3 i oc4 i ocl3 i ocl2 i ocl1 t oc1 t oc2 t oc3 t oc4 t oc5 t oc6 t oc7 time i ocl4 free datasheet http:///
analog integrated circuit device data ? 46 freescale semiconductor 10XSC425 the gcr register disables the overvoltage pr otection (d0). when this bits is [0], t he overvoltage is enabled (default value). 6.4.2.5 address 00111 ? calibration register (calr) the calr register allows the mcu to calib rate internal clock, as explained in figure 13 . 6.4.3 serial output communicatio n (device status return data) when the csb pin is pulled low, the output register is loaded. meanwhile, the data is clo cked out msb- (od15-) first, as the new message data is clocked into the si pin. the first sixt een bits of data clocking out of the so, and following a csb transition, is dependent upon the previ ously written spi word. any bits clocked out of the serial output (so) pin after the fi rst 16 bits will be representative of the initial message bits c locked into the si pin since the csb pin first transitioned to a logic [0]. this feature is useful for daisy chaining devices as well as message verification. a valid message length is determined following a csb transition of [0] to [1]. if there is a valid message length, the data is latched into the appropriate registers. a vali d message length is a multiple of 16 bits. at this time, the so pi n is tri-stated and the fault status register is now able to a ccept new fault status information. so data will represent information ranging fr om fault status to register contents, user selected by writing to the statr bits o d4, od3, od2, od1, and od0. the value of th e previous bits soa4 and soa3 will de termine which output the so information applies to for the registers, which ar e output specific; viz., fault, pwmr, confr0, confr1, and ocr registers. note that the so data will continue to reflect the information fo r each output (depending on the previous soa4, soa3 state) tha t was selected during the most recent statr write until changed with an updated statr write. the output status register correctly refl ects the status of the statr-selected register data at the time that the csb is pulled to a logic [0] during spi communication, and/or fo r the period of time since the last va lid spi communication, with the following exception: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred. ?the v pwr voltage is below 4.0 v, the status must be ignored by the mcu. table 21. csns reporting selection temp_en (d5) csns_en (d4) csns reporting 0 0 csns tri-stated (default) x 1 current recopy of selected output (d3:2] bits) 1 0 temperature on gnd flag table 22. output current recopy selection csns1 (d3) csns0 (d2) csns reporting 0 0 hs0 (default) 01 hs1 10 hs2 11 hs3 free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 47 10XSC425 6.4.4 serial output bit assignment the 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. table 23 , summarizes so returned data for bits od15 : od0. ? bit od15 is the msb; it reflects the state of the watchdog bit from the previously clocked-in message. ? bits od14:od10 reflect the state of the bits soa4 : soa0 from the previously clocked-in message. ? bit od9 is set to logi c [1] in normal mode (nm). ? the contents of bits od8 : od0 depend on bits d4 : d0 from the most recent statr command soa4 : soa0 as explained in the paragraphs following table 23 . table 23. serial output bit map description previous statr so returned data s o a 4 s o a 3 s o a 2 s o a 1 s o a 0 od 15 od 14 od 13 od 12 od 11 od 10 o d9 od8 od7 od6 od5 od4 od3 od2 od1 od0 statr _s a 1 a 0 0 0 0 wdi n so a4 soa 3 soa 2 so a1 so a0 n m por uv ov olon _s olof f_s os_s ot_s sc_s oc_s pwmr _s a 1 a 0 0 0 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m 28w _s on_ s pwm 6_s pwm 5_s pwm 4_s pwm3_s pwm2_s pwm1_s pwm0_s conf r0_s a 1 a 0 0 1 0 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x dir_d is_s sr1_ s sr0_s delay2_s delay1 _s delay0 _s conf r1_s a 1 a 0 0 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x retry_ unlimit ed_s retry_ dis_s os_di s_s olon_dis _s oloff_dis _s olled_ en_s csns_r atio_s ocr_s a 1 a 0 1 0 0 wdi n so a4 soa 3 soa 2 so a1 so a0 n m xeno n_s bc1 _s bc0_ s oc1_ s oc0_ s ochi_s oclo1_s oclo0_ s oc_mod e_s gcr 0 0 1 0 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m vdd _fai l_e n pw m_e n cloc k_sel temp _en csns _en csns1 csns0 x ov_dis diagr 0 0 0 1 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x x x x clock_fail cal_fail otw diagr 1 0 1 1 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x x in3 in2 in1 in0 wd_en diagr 2 1 0 1 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x x x x0 1 1 regist er state after rst = 0 or v dd(f ail) or v supp ly(por ) conditi on n/ a n/ a n/ a n/ a n/ a 0 0 0 0 0 0 0 x 0 0 0 0 00 0 0 s = output selection with the bits a 1 a 0 as defined in table 12 free datasheet http:///
analog integrated circuit device data ? 48 freescale semiconductor 10XSC425 6.4.4.1 previous address soa4 : soa0 = a 1 a 0 000 (statr_s) the returned data od8 reports logic [1] in case of previous power on reset condition (v supply(por) ). this bit is only reset by a read operation. bits od7: od0 reflect the current state of the fault register (fltr) corresponding to the ou tput previously sele cted with the bits soa4:soa3 = a 1 a 0 ( table 23 ). ? oc_s: overcurrent fault detec tion for a selected output, ? sc_s: severe short-circuit fault detection for a selected output, ? os_s: output shorted to v pwr fault detection for a selected output, ? oloff_s: openload in off state fault detection for a selected output, ? olon_s: openload in on state fault detection (depending on cu rrent level threshold: bulb or led) for a selected output, ? ov: overvoltage fault detection, ? uv: undervoltage fault detection ? por: power on reset detection. the fsb pin reports all faults. for latched faults, this pin is rese t by a new switch off command (toggling fault_control signal). 6.4.4.2 previous address soa4 : soa0 = a 1 a 0 001 (pwmr_s) the returned data contains the programmed values in the pwmr register for t he output selected with a 1 a 0 . 6.4.4.3 previous address soa4 : soa0 = a 1 a 0 010 (confr0_s) the returned data contains the programmed values in the confr0 register for th e output selected with a 1 a 0 . 6.4.4.4 previous address soa4 : soa0 = a 1 a 0 011 (confr1_s) the returned data contains the programmed values in the confr1 register for th e output selected with a 1 a 0 . 6.4.4.5 previous address soa4 : soa0 = a 1 a 0 100 (ocr_s) the returned data contains the programmed values in the ocr register for th e output selected with a 1 a 0 . 6.4.4.6 previous address soa4 : soa0 = 00101 (gcr) the returned data contains the progr ammed values in the gcr register. 6.4.4.7 previous address soa4 : soa0 = 00111 (diagr0) the returned data od2 reports logic [1] in case of pw m clock on in0 pin is out of specified frequency range. the returned data od1 reports logic [1 ] in case of calibration failure. the returned data od0 reports logic [1] in case of overte mperature prewarning (temperat ure of gnd flag is above t otwar ). 6.4.4.8 previous address soa4 : soa0 = 01111 (diagr1) the returned data od4: od1 report in real time the state of the direct input in[3:0]. the od0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). od4: od1 report the output state in c ase of fail-safe state due to watchdog ti me-out as explained in the following table 24 . table 24. watchdog activation report wd_en (od0) spi watchdog 0 disabled 1 enabled free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 49 10XSC425 6.4.4.9 previous address soa4 : soa0 = 10111 (diagr2) the returned data is the product id. bits od 2:od0 are set to 011 for protected dual 10 m ? and 25 m ? high side switches. default device configuration the default device configuration is explained by the following: ? hs output is commanded by corresponding in input or on bit through the spi. the medium slew rate is used, ? hs output is fully protected by the xenon overcurrent profile by defau lt, the severe short-circuit protection, the undervoltag e, and the overtemperature protection. the auto-retry feature is enabled, ? openload in on and off state and hs shorted to v pwr detections are available, ? no current recopy and no anal og temperature feedback active, ? overvoltage protection is enabled, ? so reporting fault status from hs0, ?v dd failure detection is disabled. free datasheet http:///
analog integrated circuit device data ? 50 freescale semiconductor 10XSC425 7 typical applications 7.1 introduction the following figure shows a typical lighting application (only on e vehicle corner) using an external pwm clock from the main mcu. a redundancy circuitry has been implemented to substitute light control (from mcu to watchdog) in case of a fail-safe condition. it is recommended to locate a 22 nf decoupling capacitor to the module connector. figure 16. typical lighting (one corner) 10XSC425 i/o v dd v dd v pwr gnd mcu voltage regulator v pwr hs2 hs0 hs1 hs3 vpwr vdd wake fs in0 in2 in3 sclk cs si so fsi rst in1 100nf i/o i/o sclk cs si so 10k 10k 10k 10k 10k 10k 3.3k 10k load 0 load 1 csns a/d v dd v dd v pwr v dd 22nf 22nf load 2 22nf load 3 22nf 22nf 10k watchdog direct light commands (pedal, comodo,...) vpwr ignition switch 100nf 10f 100nf 10f 100nf 100nf free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 51 10XSC425 8 packaging 8.1 soldering information the 10XSC425 was qualified in accordance with jedec standard s j-std-020c pb-free reflow profile. the maximum peak temperature during the soldering process should not exceed 260 c for 40 seconds maximum duration. 8.2 marking information the device is identified by the part number: 10XSC425. device markings indicate build information containing the week and year of manufacture. the date is coded with the last four characters of the nine character build information code (e.g. ?c tkah0929?). the date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the week. for instance, the date code ?1329? indicates the 29 th week of the year 2013. 8.3 package mechanical dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword sear ch for the drawing?s document number. table 25. package outline package suffix package outline drawing number 32-pin soic-ep ek 98asa00368d free datasheet http:///
analog integrated circuit device data ? 52 freescale semiconductor 10XSC425 ek suffix 32-pin soic-ep 98asa00368d issue 0 free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 53 10XSC425 ek suffix 32-pin soic-ep 98asa00368d issue 0 free datasheet http:///
analog integrated circuit device data ? 54 freescale semiconductor 10XSC425 ek suffix 32-pin soic-ep 98asa00368d issue 0 free datasheet http:///
analog integrated circuit device data ? freescale semiconductor 55 10XSC425 9 revision history revision date description of changes 1.0 8/2013 ? initial release based on the mc10xs3425 data sheet 2.0 9/2013 ? added the note ?to achieve high reliability over 10 years of continuous operation, the device's continuous operating junction te mperature should not exceed 125 ? ? c.? to operating temperature free datasheet http:///
document number: mc10XSC425 rev. 2.0 9/2013 information in this document is provided solely to enable sys tem and software implementers to use freescale products. there are no express or implied copyright licenses granted her eunder to design or fabricate any integrated circuits on the information in this document. freescale reserves the right to make changes without fu rther notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or s pecifications can and do vary in diff erent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditi ons of sale, which can be found at the following address: http://www.reg.net/v2/webservices/fr eescale/docs/termsandconditions.htm freescale and the freescale logo, are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. smartmos is a trademark of freescale semiconductor, inc. a ll other product or service names are the property of their respective owners. ? 2013 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support free datasheet http:///

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